Our Publications

Copper Electroplating process for passive Si-based System in Package applications L. Hamelin, S. Ledain...Proceedings BCTM, 2005	2013-05-15 09:33:56 319.64 KB
Full-Wave Analysis of Inhomogeneous Deep-Trench Isolation Patterning for Substrate Coupling ... Sidina Wane, Damienne Bajon. IEEEMTT Journal, December 2006	2013-05-15 09:35:01 2.62 MB
Passive and Heterogeneous Integration Techniques for 3D System-in-Package Applications Fred Roozeboom, W. Dekkers...12th Annual Pan Pacific Microelectronics Symposium Jan. 30 2007 ...	2009-12-31 13:14:20 480.59 KB
Passive and heterogeneous integration towards a Si-based System-in-Package conceptF. Roozeboom ... H. Kretschman, T. Fric... Thin Solid Films (2006), ICMAT 2005 Conf., July 3-8 2005, Singapore	2013-05-15 09:36:29 985.80 KB
Silicon-Based System-in-Package: Breakthroughs in Miniaturization and ‘Nano’-integration ... Franck Murray, François LeCornec... Mat. Res. Soc. Symp. Proc, April 19, 2007	2013-05-15 09:36:53 618.17 KB

Low profile 3D-IPD for Advanced Wafer Level Packaging S. Bellenger, C. Bunel, F. Murray, Device Packaging Conf. 2011	2013-05-15 10:04:31 235.50 KB
Low Profile Integrated Passive Devices with 3D High Density Capacitors C. Bunel, S. Borel, M. Pommier, S. Jacqueline, ESTC Conf. 2012	2013-05-15 10:05:42 688.99 KB
Physical Implentation of 3D Integrated Solenoids within Silicon Substrate for Hybrid IC ... M. Duplessis, O. Tesson, F. Neuilly, J.R. Tenailleau, P. Descamps	2013-05-03 16:34:55 372.31 KB
Silicon Capacitors with extremely high stability and reliability ideal for high temperature ... C. Bunel, L. Lengignon, HiTEC Conf. 2012	2013-05-15 10:07:11 326.54 KB
Ultra High Density Capacitors merged with Through Silicon Vias to enhance performances C. Bunel, F. Voiron, J-R. Tenailleau, Device Packaging 2013	2013-05-15 10:08:06 381.04 KB