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Performances

PASSIVE INTEGRATION TECHNOLOGIES OFFER DIFFERENTIATION AND MINIATURIZATION AS WELL AS PERFORMANCE

3D Silicon Capacitors

  • Murata's 3D silicon capacitors provide an efficient technique to design decoupling systems in the RF domain
  • Murata's 3D silicon capacitors outperform SMDs at frequencies > 1 GHz
  • The integrated capacitors can replace not only discrete capacitors on power lines but also many more capacitors in power amplifiers and other RF devices.
  • Temperature behavior

High stability over a large temperature range for our PICS Capacitor has been demonstrated.

  • Voltage behavior

Voltage stability of Murata silicon capacitor exceeds the current industry standard.

 
  • Leakage current

Leakage current is a key differentiator compared with Ta & MLCC Capacitors. Typical value is < 30 nA/µF in the normal operating voltage area.

3D Silicon Capacitors for efficient decoupling

Power distribution system noise affects computer product timing performance, signal integrity and electromagnetic interference. Between 1 MHz and 1 GHz, the primary means of reducing power distribution noise is with decoupling capacitors.

In case of discretes or SMDs, most of the inductance value is due to the mounting pad structure. Consequently, the way designer connects the device is a key factor in determination of ESL.

Since it is quite impossible to anticipate layout design during device modeling, there is considerable uncertainty in certain cases on ESL value. We clearly see that integrating the decoupling capacitors within the applications produces major advantages: significantly reduced traces and improved Self Resonance Frequency of the device.

  • Aging behavior - Failure rate of the PICS Capacitor

Operating temperature range : -55 C - 150 C
Maximum operating voltage: 3.6 V
Typical lifetime: 10 years @ 100 C
Failure in Time: 0.017 FIT @ 1 year, 10 times better than SMD

The PICS technology can be used as a platform for hetero-integration to form a Si-based System In Package using flip-chip techniques to minimize interconnect parasitics and footprint area.

 

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